[Note: this webpage last modified Friday, 04-Feb-2011 19:44:51 EST]
Something cool about theory of computing, something you can do with it...
Or, is there a problem in the book you'd like to talk about?
Today's attendance.
Review of what we did last time.
Existence of NP-complete problem - basically a problem that "encodes" the behavior of any NP verifier. And note what role the 1t played there.
Also can use this proof or a reduction to show that bounded halting is NP-complete - you will show this on the homework.
Point out that P is contained in NP by definition.
Sketch of problem 1 from hw2.
Tips: look at the HW early, ask questions (office hours, by appointment, by email, at beginning/end of class, work with your classmates), read the textbook and type in all the examples while you read.
Collect the homework, hand out the new one after class.
Can think of a problem being complete as "encoding" computation. Can have P-complete problems (in P and the "hardest problems" in P). A problem being P-complete essentially means that we could think of the problem as a "general purpose" computing device - we could solve any problem in P be translating our questions into questions about the problem. Being NP-complete, then, is like a general-purpose verifier - any "verification/search" question can be translated into a question about the NP-complete problem.
For the problem we did last time, this is not surprising - it really was an encoding of the computation of Turing machines.
The problems we do today and next time will be probably a bit more surprising that they can be used as "general purpose" verification/computation problems.
Today: Circuit Satisfiability is NP-complete.
Circuit - AND, OR, NOT gates, just like a circuit in a "real" computer. Given an input to a circuit, can efficiently evaluate the circuit just by plugging in values and evaluating the gates. Also, note that a large enough circuit can compute any function. Suppose have function from n bits to 1 bit, look at the truth table of the function, and express it as an OR of ANDs. What is the size of this circuit? Exponential.
Note that this OR of ANDs is actually a formula. Difference between a formula and a circuit is that gates in a circuit can out-degree more than 1 (this is like reusing the computation that lead up to the gate), while formulas have each gate with out-degree at most 1 (formulas look like trees when you draw them like circuits).
Circuit SAT problem: given description of Circuit, is there a setting of the input bits to the circuit that causes it to output 1 (is there a "satisfying" assignment for the circuit).
The proof idea is to turn the computation of a Turing machine into computation by a circuit. An NP problem is defined by a poly-time Turing machine verifier, and we want to change this into a poly-size Circuit verifier. And we need to do this transformation efficiently.
So let's look at the computation of a Turing machine verifier. Look at it as going from one configuration to another. Configuration is tape contents, where tape head is, and what is internal state of finite control. One way to represent this is to list for each tape cell two values - one with the contents of the tape cell and another with either "no" if the head is not currently on that tape cell, or the state of the finite control if the head is on that tape cell. And then we can look at the execution of the TM as updating this configuration each time the transition function of the TM is invoked, until it reaches an accepting state.
The nice thing about looking at the execution of the TM like this is that changes to the configuration are local. For any tape cell, we can determine what it should be just by looking at a few tape cells in the previous configuration.
We are going to let a circuit C take as input the supposedly correct values for the configuration of the machine for each time step (we call this the computation tableau). Notice that the there is a correct proof/certificate causing the TM verifier to accept iff there are inputs to the circuit C such that all of the following (i) the initial configuration is correct (input (x, y) on the tape, finite control in start state, and head at left of tape), (ii) each tape cell configuration is correct given the tape cells in the previous configuration, and (iii) the last configuration ends in the accepting state.
Claim is that each of these can be checked by the circuit. Describe these in words. Key for (ii) is that the changes in the configuration are local, so checking assertion on contantly many bits - which can be done by a constant size circuit (a larger constant, but still contant). The key for (iii) is that we can assume that the TM enters into an easily detectable accepting state - if it ever gets to an accepting state, it should move the tape head to the leftmost cell. This does not change which functions are efficiently computable and lets us easily detect accepting configurations.
Then need to verify that C is of polynomial size and can be computed efficiently given the code for a TM verifier and a polynomial bound on its running time.
Reading and what we will do next time - show that SAT (formula satisfiability) is NP-complete, and some other NP-complete problem. Showing that SAT is NP-complete is a reduction from circuit-SAT following somewhat of a similar outline - for each local part of the circuit (each gate), give a formula that is true iff the gate was computed correctly.