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		<author><name>Jkinne</name></author>
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		<id>https://cs.indstate.edu/web/index.php?title=CS_451_Architecture&amp;diff=82&amp;oldid=prev</id>
		<title>wiki_previous&gt;Znoble1 at 13:06, 18 May 2021</title>
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&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;== CS 451 Architecture ==&lt;br /&gt;
== Catalog Description ==&lt;br /&gt;
&lt;br /&gt;
Data representation, number systems and codes, gates and logic, combinational logic, sequential circuits, flip-flops, memory and storage, computer organization, microprogramming, architectures of supercomputers and micros.  Prerequisite - C or better in CS 202 and CS 303.&lt;br /&gt;
&lt;br /&gt;
== Prerequisites ==&lt;br /&gt;
Student must have knowledge of  Programming and Elementary Data Structures and&lt;br /&gt;
Boolean Algebra and Logic.&lt;br /&gt;
&lt;br /&gt;
== Standard Content ==&lt;br /&gt;
===Course Outline ===&lt;br /&gt;
The course begins with a review of Logic Circuit Design: Combinational Circuits and Sequential Circuits. Covered topics include logic gates, decoders , encoders, multiplexers, ROMs, universal gates, adders, flip-flops, latches, Karnaugh Maps, equivalent states, counters, bit pattern detectors, incrementers, multipliers, etc.&lt;br /&gt;
This is followed by the discussion of Instruction Set Architectures, and an example architecture: The Relatively Simple Computer. Basic Computer System Organization is considered : CPU, Memory, I/O units, Buses, Linear ad Two dimensional memory organizations.&lt;br /&gt;
Hardware description using RTL and methods of implementing RTL code are described.&lt;br /&gt;
Next is the coverage of CPU Design: Registers, Instruction Sets, State diagrams, RTL Code, design of&lt;br /&gt;
register section, control units, ALUs, and generation of control signals are covered. This is the hardwired control approach.&lt;br /&gt;
Also covered are Microprogrammed Control and its variations: Horizontal Microcode, Vertical Microcode, and string control signals in the  ROM.&lt;br /&gt;
Next comes the coverage of Cache memory organization, and virtual memory. Topics covered are associative memory, and the associative , direct and set associative mappings and LRU and FIFO cache replacement strategies, and a simulation and estimation of hit ratios. Paging is covered in detail for implementing virtual memory, and a brief coverage of segmentation is provided.&lt;br /&gt;
Input/output is considered: polling, wait states, interrupt driven I/O, vectored interrupts, and Daisy Chaining, DMA transfers and transfer modes and I/O channels are covered.&lt;br /&gt;
CISC and RISC computers and pipelining are covered next.&lt;br /&gt;
Finally, an introduction to parallel and alternative computer architectures is given.&lt;br /&gt;
&lt;br /&gt;
===Learning Outcomes===&lt;br /&gt;
A  knowledge of the working of a simple computer.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
===Important Assignments and/or Exam Questions===&lt;br /&gt;
Assignments include chapter summaries of textbook chapters ;  pencil and paper quizzes are given over the course content.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
=== Standard resources ===&lt;br /&gt;
Computer Systems Organization and Architecture by John D. Carpinelli (Addison-Wesley, 2000, ISBN-10: 0-201-61253-4)&lt;/div&gt;</summary>
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